The present invention relates to identifying the device ID and revision number of an integrated circuit, and particularly to providing an electronically readable ID and revision number in a universal asynchronous receiver/transmitter (UART) chip.
Integrated circuit parts are typically identified with a device ID and a revision number. A device ID may distinguish between multiple IC's which are similar, but have different combinations of features corresponding to different price ranges or speeds, for instance. Additionally, each particular product ID may go through multiple revisions. For example, when a bug is discovered in a chip, it can be fixed and a new revision of the chip produced. It is desirable to provide a revision number which can identify the chip to be able to distinguish one revision from another in order to determine which bugs have been fixed.
One method for doing this is to electronically encode a device ID and revision number on the chip itself at a register address, and read it by addressing that register. This method may be viable for a chip, such as a microprocessor, with a large number of address lines and potential register locations.
However, for some other chips, such as a UART chip, there may be only a few address lines (i.e., 3), and thus register space is very limited. In such applications, it is more typical for a label or etching to be placed on the bottom of the chip package. This label can then be visually observed by the user. However, if the chip has been soldered onto a board, this can become problematic.